$iPad{iELANA - } iELANA - Circuit example

For a better understanding of iELANA's macro language, we'll discuss briefly one of the sample files provided:

In the samples folder of the application you'll find the following file:
Passive double-T filter

The complete circuit diagram, drawn in a probably well known form, looks like this:


The voltage identifier Ue designates the input gate of the circuit. We'll configure this one with the voltage source, which will be used later to calculate the cicuit within the parameterized frequency range. Ue will be setup to a value of 1 V. On the very left edge we find the voltage identifier Ua, which designates the output gate of the circuit. That's the place to read out the results after the calculation of the circuit. Between Ue and Ua we have a RC circuit network which is layed out symmetrical.

It is not possible to enter these two T-parts into iELANA directly with the macro editor. A dipole reduction is not feasible without a little preliminary work.

What we will do: we decompose the filter into two sub-networks with correspondingly fewer nodes. Then we switch these two sub-networks in parallel. The first sub-network looks like this:


Now let's look at the first part of the macro list, which is loaded with our opened circuit:

U0 = 1 V
Memory #00
Cs = 4,7 nF
Rp = 8,2 kΩ
Cs = 4,7 nF

U0 corresponds to our input voltage Ue. As we'll see, we need this power source once again later. We can save ourselves from entering its value a second time by saving U0 with the command Memory #00.

As computable dipole, currently only the voltage source U0 is visible. It follows a capacitor in series (Cs). Then, a resistor is connected in parallel (Rp). It follows a second capacitor in series (Cs). It should be noted that the two capacitors have the same values. The first dipole network is now complete. In order to build a second, independent network, we place the first one on the calculation stack (Store). At the same time this ensures that a new, empty calculation dipole is provided.

Let's go on with the second sub-network. This looks like this:


This part of the plan belongs to the second part of the macro list from the open circuit:

ADDser #00
Rs = 16,4 kΩ
Cp = 9,4 nF
Rs = 16,4 kΩ

To get started building the network, we need again the voltage source Ue. We stored this one at the beginning into a fixed memory. Because a voltage source is a serial element, we insert it from our fixed memory into the new sub-network using ADDser #00. It is followed by a resistor in series (Rs). Added, a capacitor connected in parallel (Cp), and at the end, another resistance in series (Rs). On the diagram we see that the resistors have the same values. They are twice as big as in the first sub-network. The capacitor has also twice the value of the first sub-network.

The first sub-network is stored on a calculation stack yet. To complete the circuit now, we connect both sub-networks in parallel:


The makro command Parallel causes a parallel connection of the current calculation dipole with the dipole stored in the subsequent calculation stack to be executed. The macro END terminates the circuit. It indicates the output of the circuit at which the desired output quantities to be expected.

At the given dimensions of the components, the filter has a cutoff frequency between 2.06 kHz and 2.07 kHz.

Copyright © 2015,2016 by Konran Udo Gerber

@!A version @!V (@!T) build
iOS SDK: @!L // Device iOS: @!D
running @!C-bit code
CPU type: @!U

Last changed: February 2, 2015 3:01 AM